1 DN3125 03/03/99 supertex inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. no responsibility is assumed for possible omissions or inaccuracies. circuitry and specifications are subject to c hange without notice. for complete liability information covering this and other supertex products, refer to the supertex 1998 databook. DN3125 advanced dmos technology these low threshold depletion-mode (normally-on) transistors utilize an advanced vertical dmos structure and supertexs well-proven silicon-gate manufacturing process. this combina- tion produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and posi- tive temperature coefficient inherent in mos devices. character- istic of all mos structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. * die in wafer form. features high input impedance low input capacitance fast switching speeds low on resistance free from secondary breakdown low input and output leakage applications normally-on switches solid state relays converters linear amplifiers constant current sources power supply circuits telecom n-channel depletion-mode vertical dmos fets bv dsx /r ds(on) i dss bv dgx (max) (min) die* 250v 20 w 200ma DN3125nw ordering information order number / package absolute maximum ratings drain-to-source voltage bv dsx drain-to-gate voltage bv dgx gate-to-source voltage 20v operating and storage temperature -55 c to +150 c new product
2 DN3125 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t. t (on) t d(on) t (off) t d(off) t f t r input input output 0v v dd r gen 0v -10v switching waveforms and test circuit electrical characteristics (@ 25 c unless otherwise specified) notes: 1. all d.c. parameters 100% tested at 25 c unless otherwise stated. (pulse test: 300 m s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. symbol parameter min typ max unit conditions bv dsx drain-to-souce breakdown voltage 250 v v gs = -5.0v, i d = 100 m a v gs(off) gate-to-source off voltage -1.5 -3.5 v v ds = 15v, i d = 10 m a d v gs(off) change in v gs(off) with temperature 4.5 mv/ cv ds = 15v, i d = 10 m a i gss gate body leakage current 100 na v gs = 20v, v ds = 0v i d(off) drain-to-source leakage current 1.0 m av gs = -5.0v, v ds = max rating 1.0 ma v gs = -5.0v, v ds = 0.8 max rating t a = 125 c i dss saturated drain-to-source current 200 ma v gs = 0v, v ds = 15v r ds(on) static drain-to-source 20 w v gs = 0v, i d = 150ma on-state resistance 20 v gs = -0.8v, i d = 50ma d r ds(on) change in r ds(on) with temperature 1.1 %/ cv gs = 0v, i d = 150ma g fs forward transconductance 150 m m i d = 100ma, v ds =10v c iss input capacitance 60 120 c oss common source output capacitance 6.0 15 pf v gs = -5.0v, v ds = 25v, c rss reverse transfer capacitance 3.0 10 f =1.0mhz t d(on) turn-on delay time 10 ns v dd = 25v, t r rise time 15 i d = 150ma, t d(off) turn-off delay time 15 r gen = 25 w , t f fall time 20 v gs = 0v to -10v v sd diode forward voltage drop 1.8 v v gs = -5.0v, i sd = 150ma t rr reverse recovery time 800 ns v gs = -5.0v, i sd = 150ma 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 744-0100 ? fax: (408) 222-4895 www.supertex.com 03/03/99 w
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